Exemplary embodiments of the present invention relate to a semiconductor device, a memory system, and a method for controlling a termination operation of the same.
A memory device includes termination circuits configured to terminate interface pads inside the memory device, in order to perform a high-speed operation. It means, for example, that the termination circuits adjust impedance/resistant of the interface pad for an impedance matching at an interface stage. The interface pads may include a data (DQ) pad and a data strobe signal (DQS) pad. The termination circuit is controlled to be turned-on/off or to change a termination resistance value through an on-die termination (ODT) pin, thereby minimizing a jitter effect occurring in the interface stage.
FIG. 1 is a configuration diagram of a conventional memory system.
Referring to FIG. 1, the memory system includes a memory controller 110 and a memory device 120.
The memory controller 110 applies a command CSB, RASB, CASB, and WEB for controlling the memory device 120 and an on-die termination (ODT) signal ODT for controlling the turn-on/off of a termination circuit of the memory device 120.
The memory device 120 decodes the applied command CSB, RASB, CASB, and WEB and performs a variety of operations such as read and write operations. When the ODT signal ODT is activated, the memory device 120 enables the termination circuit inside the memory device 120 in response to the ODT signal ODT. When the ODT signal ODT is deactivated, the memory device 120 disables the termination circuit inside the memory device 120 in response to the ODT signal ODT.
Between the memory controller 110 and the memory device 120, a data channel, an address channel and so on may be formed in addition to the command channels and the ODT signal channel. FIG. 1 omits the data channel and the address channel for the convenience of the description.
FIG. 2 is a timing diagram showing that the termination circuit is controlled to be turned on/off through the ODT pin during the read operation of the memory device.
Referring to FIG. 2, during the initial period in which the ODT signal ODT is activated to high level, the termination circuit terminates an interface pad with a default termination resistance value Rtt_default. That is, the termination circuit controls a termination resistance value with the default termination resistance value Rtt_default. In FIG. 2, a signal Rterm represents the operation of the termination circuit.
Then, a read command RD is applied. After a time corresponding to CAS latency (CL) elapses from the application time of the read command RD, a data strobe signal DQS is toggled, and data DQ is inputted. While the data DQ is inputted, the termination circuit is to be turned off.
Therefore, after a certain time (e.g., two clocks) elapses after the application of the read command RD, the ODT signal ODT is deactivated to low level, and the termination circuit is turned off in response to the ODT signal ODT. When the ODT signal ODT is activated to high level, the termination circuit is turned on in response to the ODT signal ODT. A time difference between the activation/deactivation of the ODT signal and the turn on/off of the termination circuit is defined by JEDEC SPEC. In the case of the DDR3 memory device, such a time difference is defined as clocks smaller than the clocks corresponding to CAS write latency (CWL) by 2 clocks.
As described above with reference to FIG. 2, the turn on/off of the termination circuit in the memory device is controlled by the activation/deactivation of the ODT signal.
FIG. 3 is a timing diagram showing a dynamic ODT operation of the memory device.
The dynamic ODT operation refers to an operation which automatically changes the termination resistance value of the termination circuit during a period in which data DQ is inputted in response to an applied write command WR without resetting the termination resistance value by a mode resister set (MRS) or the like.
Referring to FIG. 3, the ODT signal ODT continuously maintains the activation to high level. Therefore, the termination circuit maintains the turn-on state. During the initial period of FIG. 3, the termination resistance value is maintained to a default termination resistance value (Rterm=Rtt_default). However, when the write command WR is applied, the data strobe signal DQS is toggled in response to the write command WR. During a period in which the data DQ is inputted, the termination resistance value is changed into a termination resistance value Dynamic ODT by the dynamic ODT operation. That is, the termination circuit maintains the default termination resistance value Rtt_default of 30 or 40Ω during the initial period, and the default termination resistance value Rtt_default is changed into the termination resistance value Dynamic ODT of 60 or 120Ω during the period in which the data DQ is inputted in response to the write command WR.
As described above with reference to FIG. 3, the change of the termination resistance value among the operations of the memory device may be controlled by the write command WR.
FIG. 4 is a command decoding truth table of the DDR3 memory device defined in JEDEC.
FIG. 4 shows combinations of command signals and decoding results based on the combinations. For example, a combination of CSB=L, RASB=H, CASB=L, and WEB=L is applied to the memory device, the memory device decodes the combination and recognizes the decoded combination as a write command WR.
The functions defined in FIG. 4 may be represented as follows.
MRS represents Mode Register Set, REF represents Refresh, SRE represents Self Refresh Entry, SRX represents Self Refresh Exit, PRE represents Single-bank Precharge, PREA represents Precharge all bank, ACT represents Bank Active, WR represents Write, WRA represents Write with auto precharge, RD represents Read, RDA represents Read with auto precharge, NOP represents No Operation, DES represents Device Deselected, PDE represents Power-Down Entry, PDX represents Power-Down Exit, ZQCL represents ZQ Calibration long, and ZQCS represents ZQ Calibration Short.
The functions and signals of the truth table of FIG. 4 are apparent to those skilled in the art to which the present invention pertains. Therefore, the description thereof is omitted.
FIG. 5 is an internal configuration diagram of the conventional memory device.
In FIG. 5, blocks CSB, CASB, RASB, and WEB represent buffers configured to receive the respective command signals, a block CK represents a buffer configured to receive a clock signal, a block ADDR represents a buffer configured to receive an address, and a block ODT represents a buffer configured to receive an ODT signal. A block DQS represents a buffer configured to receive a data strobe signal, and a block DQ represents a circuit block configured to receive and output data. The blocks DQ and DQS may include termination circuits, because the blocks DQ and DQS have channels with external memory controllers. Blocks LAT represent latch circuits configured to latch the signals inputted to the buffers, and a block DLL represents a delay-locked loop circuit. A block CMD DEC & CTRL represents a control circuit configured to decode a command to control the operation of the memory device, and a block ODT CTRL represents a control circuit configured to control the turn on/off of the termination circuit by using the ODT signal. A block S2P/P2S represents a circuit configured to parallel-to-serial convert or serial-to-parallel convert the data inputted/outputted through the circuit block DQ. A block GIO Driver represents a circuit configured to transfer data between the block S2P/P2S and a block Column, the block Column represents a circuit for a column operation of a block CORE, and a block ROW represents a circuit for a row operation of the block CORE. The block CORE represents a core area of the memory device in which the data is stored.
Referring to FIG. 5, the termination operation of the conventional memory device is described. The ODT signal inputted through the buffer ODT is latched by the latch circuit LAT and transferred to the block ODT CTRL. When the ODT signal is activated, the block ODT CTRL turns on the termination circuits of the blocks DQS and DQ in response to the ODT signal. When the ODT signal is deactivated, the block ODT CTRL turns off the termination circuits of the blocks DQS and DQ in response to the ODT signal. As such, the turn-on/off of the termination circuits are controlled by the block ODT CTRL which operates by receiving the ODT signal inputted through the buffer.
The command signals inputted through the respective buffer CSB, CASB, RASB, and WEB are latched by the respective latch circuits LAT and transferred to the block CMD DEC & CTRL. The block CMD DEC & CTRL decodes the command signals. Depending on the decoding result, when it is determined that the write command WR is applied, the block CMD DEC & CTRL changes the termination resistance values of the termination circuits inside the blocks DQS and DQ. As such, the change of the termination resistance values of the termination circuits is controlled by the block CMD DEC & CTRL which operates by receiving the command signals.
As described with reference to FIGS. 2, 3, and 5, the control of the turn on/off of the termination circuits and the change of the termination resistance values of the termination circuits in the conventional memory system are performed in different manners from each other. That is, the control of the termination circuit by the ODT signal inputted through the ODT pin and the control of the termination resistance values by the command signals are used together. This may cause the complexity of the data with which the memory controller controls the memory device. Furthermore, the design of the memory device may become complex.